honestly, risc-v may not be the Future(tm)
mostly because it's simple, too simple: so while simple implementations of risc-v can be made simply, high performance implementations are much more trickier, since it's fairly hard to map simple, single-purpose instructions into the multiple-specific-purpose-execution-engines model of modern processors
so any performant risc-v implementation would need a complex out-of-order, superscalar, speculative scheduler, which as has been shown recently, is a complete security clusterfuck
mostly because it's simple, too simple: so while simple implementations of risc-v can be made simply, high performance implementations are much more trickier, since it's fairly hard to map simple, single-purpose instructions into the multiple-specific-purpose-execution-engines model of modern processors
so any performant risc-v implementation would need a complex out-of-order, superscalar, speculative scheduler, which as has been shown recently, is a complete security clusterfuck
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Oh my, i don’t know much about systems engineering.
But i did hear that there are quite a few startups that have invested heavily in this architecture.
Is this really doomed from the start? Or just a pain in the arse to implement?
