Fact 1: RISC-V is based on extensions
Fact 2: All RISC-V extensions are optional
Fact 3: RISC-V extensions may vary between CPUs
Fact 4: Programs would like to know what extensions the CPU supports
Fact 5: RISC-V provides an instruction to get all supported extension
Fact 6: Programs can't use the instruction to get all supported extensions because said extension is part of the privileged instruction set, WHICH REGULAR PROGRAMS CAN'T USE!
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Fact 2: All RISC-V extensions are optional
Fact 3: RISC-V extensions may vary between CPUs
Fact 4: Programs would like to know what extensions the CPU supports
Fact 5: RISC-V provides an instruction to get all supported extension
Fact 6: Programs can't use the instruction to get all supported extensions because said extension is part of the privileged instruction set, WHICH REGULAR PROGRAMS CAN'T USE!
!!
!!!!
!!!!!!!
!!!!!!!!!!
@lynne that's RISC-V for you.
They tried to make ISA without designing a chip or targetting one market.
It's like we've got ARM 2 with all its downsides.
They tried to make ISA without designing a chip or targetting one market.
It's like we've got ARM 2 with all its downsides.
i guess you're supposed to forward it from the os?
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@icedquinn @a1ba @lynne
Sounds like a real *RISC* to me ;P
