@lupyuen the patch introduces a new function called `flush_icache_range_phy` that flushes the instruction cache for a given range of physical addresses. It uses assembly instructions to perform the cache flushing operation. additionally, `flush_icache_range` macro is modified to call the new `flush_icache_range_phy` function instead of `flush_icache_all`
It's likely that the T-Head C9xx processor has its own cache synchronization mechanism tailored to its specific architecture and requirements
@lupyuen generally, in a multi-level cache hierarchy, such as the one in the T-Head C9xx processor, it's crucial to maintain data consistency between different levels of cache (because modifications to data can be made in one level of cache and need to be propagated to other levels to ensure that all caches have the most up-to-date version of the data). Cache sync typically involves two main operations: cache invalidation and cache flushing
