Lup Yuen Lee 李立源 @lupyuen@social.cleverlibre.org

Here's how we enable Strong Ordering for Memory Mapped I/O ... On #Ox64 BL808 and T-Head C906

Article: https://lupyuen.codeberg.page/articles/plic3.html#enable-strong-order

Why is TCC #RISCV Compiler hitting "Unknown Relocation Type 60"? 🤔

Source: https://github.com/lupyuen/tcc-riscv32-wasm#fix-missing-printf-in-nuttx-app

Inside the Memory Management Unit of #Ox64 BL808 SBC ... And how it controls Strong Ordering

Article: https://lupyuen.codeberg.page/articles/plic3.html#memory-management-unit

TCC Compiler Output (from #WebAssembly) prints "Hello World" in Apache #NuttX RTOS! 🎉 ... But needs painful #RISCV Assembly 🤔

Source: https://github.com/lupyuen/tcc-riscv32-wasm#ecall-for-nuttx-system-call

Here's how Apache #NuttX RTOS links a NuttX App

Source: https://github.com/lupyuen/tcc-riscv32-wasm#how-nuttx-build-links-a-nuttx-app

TCC Compiler in WebAssembly has generated a #RISCV ELF ... Let's run it on Apache #NuttX RTOS!

Source: https://github.com/lupyuen/tcc-riscv32-wasm#test-tcc-output-with-nuttx

Implementing printf() in #ZigLang with Pattern Matching ... So TCC Compiler will run in #WebAssembly 🤔

Source: https://github.com/lupyuen/tcc-riscv32-wasm#fix-the-varargs-functions

#RISCV T-Head C906 Errata in Linux Kernel ... Says that we need Strong Ordering for I/O Memory in #Ox64 BL808 SBC

Article: https://lupyuen.codeberg.page/articles/plic3.html#t-head-errata

Barebones TCC #RISCV Compiler in #WebAssembly 🎉

Source: https://lupyuen.github.io/tcc-riscv32-wasm/

#Ox64 BL808 UART Controller has Leaky Reads and Writes ... But there's a simple fix!

Article: https://lupyuen.codeberg.page/articles/plic3.html#leaky-reads-in-uart

TCC #RISCV Compiler, compiled to #WebAssembly by #ZigLang Compiler ... Generates correct ELF Code! 🎉

Source: https://github.com/lupyuen/tcc-riscv32-wasm#tcc-webassembly-runs-ok-in-a-web-browser

Running TCC #RISCV Compiler inside the Web Browser ... Thanks to #ZigLang Compiler 👍

Source: https://github.com/lupyuen/tcc-riscv32-wasm#test-the-tcc-webassembly-in-a-web-browser

Strange problems in #Ox64 BL808 UART and Interrupt Controller ... Let's investigate the alligator in the vest

Article: https://lupyuen.codeberg.page/articles/plic3.html#uart-and-plic-troubles

TCC: The simple C Compiler for #RISCV ... Can we compile TCC to #WebAssembly with #ZigLang Compiler? 🤔

Source: https://github.com/lupyuen/tcc-riscv32-wasm

"expect" script works OK for testing our #Ox64 BL808 Emulator 🎉

Source: https://github.com/lupyuen/nuttx-tinyemu

Here's how we handle a UART Interrupt on #Ox64 BL808 #RISCV SBC

Article: https://lupyuen.codeberg.page/articles/plic3.html#uart-interrupt

Try our Online Demo of Apache #NuttX Real-Time Operating System ... Powered by TinyEMU #RISCV Emulator 👍

Source: https://nuttx.apache.org/demo/

Weak Ordering in the #Ox64 BL808 Memory Management Unit (#RISCV T-Head C906) ... Causes problems with the UART and Interrupt Controllers! Here's how we fix it

Article: https://lupyuen.codeberg.page/articles/plic3

Fixed the MMU Cache for #Ox64 BL808 #RISCV SBC on Apache #NuttX RTOS 👍

Source: https://github.com/apache/nuttx/pull/11585

Remember to Flush the MMU Cache when switching Page Tables ... On #RISCV T-Head C906 and #Ox64 BL808 SBC

Article: https://lupyuen.codeberg.page/articles/mmu.html#appendix-flush-the-mmu-cache-for-t-head-c906