Here's how we handle a UART Interrupt on #Ox64 BL808 #RISCV SBC
Article: https://lupyuen.codeberg.page/articles/plic3.html#uart-interrupt
Strange problems in #Ox64 BL808 UART and Interrupt Controller ... Let's investigate the alligator in the vest
Article: https://lupyuen.codeberg.page/articles/plic3.html#uart-and-plic-troubles
#Ox64 BL808 UART Controller has Leaky Reads and Writes ... But there's a simple fix!
Article: https://lupyuen.codeberg.page/articles/plic3.html#leaky-reads-in-uart
#RISCV T-Head C906 Errata in Linux Kernel ... Says that we need Strong Ordering for I/O Memory in #Ox64 BL808 SBC
Article: https://lupyuen.codeberg.page/articles/plic3.html#t-head-errata
Here's how we enable Strong Ordering for Memory Mapped I/O ... On #Ox64 BL808 and T-Head C906
Article: https://lupyuen.codeberg.page/articles/plic3.html#enable-strong-order
After enabling Strong Ordering on #Ox64 BL808 ... Our UART and Interrupt troubles are finally over!
Article: https://lupyuen.codeberg.page/articles/plic3.html#it-works
#RISCV T-Head C906 works hunky dory ... Just be careful 👍
Article: https://lupyuen.codeberg.page/articles/plic3.html#lessons-learnt
@lupyuen thank you for writing this up. I will give it a read. I have a T-Head board, though I need to find time. 
@m0jek Thanks for reading! :-)
Inside the Memory Management Unit of #Ox64 BL808 SBC ... And how it controls Strong Ordering
Article: https://lupyuen.codeberg.page/articles/plic3.html#memory-management-unit