Weak Ordering in the #Ox64 BL808 Memory Management Unit (#RISCV T-Head C906) ... Causes problems with the UART and Interrupt Controllers! Here's how we fix it

Article: https://lupyuen.codeberg.page/articles/plic3

Here's how we handle a UART Interrupt on #Ox64 BL808 #RISCV SBC

Article: https://lupyuen.codeberg.page/articles/plic3.html#uart-interrupt

Strange problems in #Ox64 BL808 UART and Interrupt Controller ... Let's investigate the alligator in the vest

Article: https://lupyuen.codeberg.page/articles/plic3.html#uart-and-plic-troubles

#Ox64 BL808 UART Controller has Leaky Reads and Writes ... But there's a simple fix!

Article: https://lupyuen.codeberg.page/articles/plic3.html#leaky-reads-in-uart

#RISCV T-Head C906 Errata in Linux Kernel ... Says that we need Strong Ordering for I/O Memory in #Ox64 BL808 SBC

Article: https://lupyuen.codeberg.page/articles/plic3.html#t-head-errata

Inside the Memory Management Unit of #Ox64 BL808 SBC ... And how it controls Strong Ordering

Article: https://lupyuen.codeberg.page/articles/plic3.html#memory-management-unit

Here's how we enable Strong Ordering for Memory Mapped I/O ... On #Ox64 BL808 and T-Head C906

Article: https://lupyuen.codeberg.page/articles/plic3.html#enable-strong-order

After enabling Strong Ordering on #Ox64 BL808 ... Our UART and Interrupt troubles are finally over!

Article: https://lupyuen.codeberg.page/articles/plic3.html#it-works